1. Field of the Invention
The present invention relates to a clock supply circuit that supplies clock signals to a built-in sequential circuit of a semiconductor integrated circuit and to a semiconductor system comprising the same. Particularly, the present invention relates to a gated clock technique for reducing power consumption of the circuit.
2. Description of the Related Art
Recently, a semiconductor integrated circuit faces a problem of power consumption that is increased in accordance with increased scale and speed thereof. Conventionally, there is known a technique called a gated clock for reducing the power consumption. In a circuit using this technique, if it is unnecessary to supply a clock signal to a certain sequential circuit (memory cell), the clock signal to be supplied to the sequential circuit is fixed to high level or low level. An example may be a case where it is clear that the stored content of a flip flop will not be updated even if the clock signal is supplied. With this, it enables reduction in the number of changes of the clock signals, thereby allowing a decrease in the circuit power consumption.
FIG. 15 is an illustration for showing the structure of a conventional clock supply circuit. A clock supply circuit 1 shown in FIG. 15 comprises buffers 11-16, and an AND gate 20 as a clock gate circuit. The clock supply circuit 1 comprises four clock paths starting from the buffer 11 and reaching flip flops F1-F4.
A clock signal CK propagated on the clock paths and an enabling signal EN for controlling propagation of the clock signal CK are inputted to the AND gate 20. When the enabling signal is “1”, the AND gate 20 lets through the clock signal CK. Thus, the clock signal CK reaches the flip flops F3 and F4 via the buffers 15 and 16. In the meantime, when the enabling signal is “0”, output of the AND gate is fixed to “0”. Thus, the clock signal CK does not reach the flip flops F3 and F4. By fixing the enabling signal to “0” in this way, it is possible to reduce the number of changes in the clock signal CK and decrease the circuit power consumption.
In the clock supply circuit 1, a NOR gate may be used instead of the AND gate 20. The NOR gate lets through the clock signal CK when the enabling signal EN is “0”, and intercepts the clock signal CK when the enabling signal EN is “1”.
The clock supply circuit having a gated clock function has such a problem that there is a large difference in delay time (clock skew) until reach of the clock signals, which is generated between the flip flops connected at the terminal ends of each clock path. Therefore, a conventional clock circuit disclosed in Japanese Patent Literature (Japanese Patent No. 3178371) employs a method in which the clock paths are formed with the same length and same stages and a group of flip flops is allotted to each clock path equally for suppressing the clock skew. With this, clock skew caused by the difference between the clock paths can be suppressed.
In the recent semiconductor integrated circuit, it becomes necessary to cope with clock skew caused by deterioration of the transistor with time in addition to the above-described clock skew caused by the difference between the clock paths. However, the conventional clock supply circuit is not designed to deal with the clock skew caused by the deterioration of the transistor occurred with time.
In the followings, there is described a reason for generation of clock skew due to deterioration with time occurred in a PMOS transistor. It is known that a PMOS transistor included in a semiconductor integrated circuit deteriorates with time due to negative bias temperature instability (NBTI). NBTI is a phenomenon of an increase in the threshold voltage and a decrease in the current capacity of the PMOS transistor, which is caused when fixed electric charges are formed by dissociation of hydrogen present in the interface between a gate insulating film and a silicon substrate under the state where the PMOS transistor is ON at a high temperature (for example, the source voltage and drain voltage are 0V and the gate voltage is negative bias).
By referring to FIG. 16 and FIG. 17, influences of NBTI exerted on the clock supply circuit will be described. FIG. 16 is a block diagram of the clock paths including the clock gate circuit. Let us look into a case where a clock signal CK with a duty ratio of 50% is inputted to the circuit shown in FIG. 16 for a prescribed time T, and the enabling signal EN for gating the clock is set as “0”. In this case, the states of nodes N1-N3 alternately repeat “0” and “1”, and PMOS transistors QP1, QP2 both become ON (i.e. the input signal becomes “0”) for a time T/2. As described, the PMOS transistors QP1 and QP2 both receive the influence of NBTI for the time T/2. Thus, the current capacities of the PMOS transistors QP1 and QP2 deteriorate for the same amount from the initial state.
Meanwhile, when the enabling signal EN is “0”, the states of the nodes N4, N5 and N6 are fixed to “0”, “1”, and “0, respectively. At this time, the PMOS transistor QP4 is always OFF, thus receiving no influence from NBTI. However, the PMOS transistor QP3 is always ON so that it receives an influence from NBTI for the time T. Accordingly, the current capacity of the PMOS transistor QP4 does not deteriorate at all but that of the PMOS transistor QP3 deteriorates tremendously.
FIG. 17 is a signal waveform diagram of an input/output signal when the enabling signal is set to high level after the time T has passed and a clock is supplied to the nodes N1-N6 in the circuit of FIG. 16.
In FIG. 17, rise delay time (Tp1 and Tp3) of the node N2 and the node N5 depends on the current capacities of the PMOS transistors QP1 and QP3, respectively, and fall delay time (Tn1 and Tn3) of the node N2 and the node N5 depends on the current capacities of the NMOS transistors QN1 and QN3, respectively. Rise delay time (Tp2 and Tp4) of the node N3 and the node N6 depends on the current capacities of the PMOS transistors QP2 and QP4, respectively, and fall delay time (Tn2 and Tn4) of the node N3 and the node N6 depends on the current capacities of the NMOS transistors QN2 and QN4, respectively.
As described above, the current capacities of the PMOS transistors QP1 and QP2 deteriorate for the same amount from the initial state, the current capacity of the PMOS transistor QP4 does not deteriorate at all, and the current capacity of the PMOS transistor QP3 deteriorates tremendously. Therefore, when each rise delay time (Tp1, Tp2, Tp3, and Tp4) in the initial state is the same, the relation between the four kinds of rise delay time after the time T can be expressed by a following expression (1).Tp4<Tp1=Tp2<Tp3  (1)
Further, as shown in FIG. 17, rise delay time Tr1 from N1 to N3 is (Tn1+Tp2), fall delay time Tfl is (Tp1+Tn2), rise delay time Tr2 from N4 to N6 is (Tn3+Tp4), and fall delay time Tf2 is (Tp3+Tn4). Thus, at the initial state and the state after the time T has passed, a following expression (2) can be found from the above-described expression (1) provided that the four kinds of rise delay time (Tn1, Tn2, Tn3, and Tn4) are the same.Tr2<Tr1=Tf1<Tf2  (2)
In the case where there are two same partial circuits (for example, the circuit shown in FIG. 15) included in the clock supply circuit, it can be seen from the expression (2) that delay time of the two partial circuits is consistent with each other at the initial state but differs as the time passes when the clock signal is constantly supplied to one of the partial circuit and a clock fixed signal is mainly supplied to the other partial circuit.
For example, in the clock supply circuit 1 shown in FIG. 15, when the clock signal CK is supplied for a certain length of time while the enabling signal EN is set as “0”, there generates clock skew between the flip flops F1 and F3 even though there is no clock skew in the initial state between the flip flops F1 and F3.
As described, in the clock supply circuit having a gated clock function, there increases the clock skew as the time passes between the flip flop to which the clock signal is supplied constantly and the flip flop to which the clock fixed signal is mainly supplied. The clock skew gradually increases while the semiconductor integrated circuit is in normal operation.